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| MC74HCT74A Dual D Flip-Flop with Set and Reset with LSTTL Compatible Inputs High-Performance Silicon-Gate CMOS The MC74HCT74A is identical in pinout to the LS74. This device may be used as a level converter for interfacing TTL or NMOS outputs to High Speed CMOS inputs. This device consists of two D flip-flops with individual Set, Reset, and Clock inputs. Information at a D-input is transferred to the corresponding Q output on the next positive going edge of the clock input. Both Q and Q outputs are available from each flip-flop. The Set and Reset inputs are asynchronous. http://onsemi.com MARKING DIAGRAMS 14 PDIP-14 N SUFFIX CASE 646 MC74HCT74AN AWLYYWW 1 14 SOIC-14 D SUFFIX CASE 751A HCT74A AWLYWW * * * * * * * Output Drive Capability: 10 LSTTL Loads TTL NMOS Compatible Input Levels Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 4.5 to 5.5 V Low Input Current: 1.0 A In Compliance with the Requirements Defined by JEDEC Standard No. 7A Chip Complexity: 136 FETs or 34 Equivalent Gates LOGIC DIAGRAM RESET 1 DATA 1 CLOCK 1 SET 1 RESET 2 DATA 2 CLOCK 2 SET 2 1 2 3 4 13 12 11 10 9 8 Q2 PIN 14 = VCC PIN 7 = GND 5 6 1 A = Assembly Location WL or L = Wafer Lot YY or Y = Year WW or W = Work Week PIN ASSIGNMENT RESET 1 DATA 1 CLOCK 1 SET 1 Q1 Q1 GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC RESET 2 DATA 2 CLOCK 2 SET 2 Q2 Q2 Q1 Q1 FUNCTION TABLE Inputs Set Reset Clock Data L H L H H H H H H L L H H H H H X X X X X X H L X X X Outputs Q Q H L L H H* H* H L L H No Change No Change No Change Q2 Design Criteria Value 34 Units ea. ns L H (c) Semiconductor Components Industries, LLC, 1999 March, 2000 - Rev. 8 II IIIIIIIIIIIIIII IIIIIIIIIIIIII II II IIIIIIIIIIIIIII III I I IIIIIIIIIIIIIII II III I II IIIIIIIIIIIIIII II IIIIIIIIIIIIIII II IIIIIIIIIIIIIII IIIIIIIIIIIII IIIIIIIIIIIIIII II I IIIIIIIIIIIIIII IIIIIIIIIIIII I Internal Gate Count* Internal Gate Propagation Delay Internal Gate Power Dissipation Speed Power Product 1.5 5.0 W pJ .0075 *Equivalent to a two-input NAND gate. 1 *Both outputs will remain high as long as Set and Reset are low, but the output states are unpredictable if Set and Reset go high simultaneously. ORDERING INFORMATION Device MC74HCT74AN MC74HCT74AD MC74HCT74ADR2 Package PDIP-14 SOIC-14 SOIC-14 Shipping 2000 / Box 55 / Rail 2500 / Reel Publication Order Number: MC74HCT74A/D MC74HCT74A III I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I III I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIII I I I I II I I I I I I I IIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I III I I I I I II I I I II I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I II I I II I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II II I I I I I III I I I I I II I I I II I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III I I I I I II I I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I II I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I II I II I II IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIII I I II I II I I IIIIIIIIIIIIIIIIIIIIIII IIII I I IIIIIIIIIIIIIIIIIIIIIII III I II I II I I II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII III I II I II I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII I II I I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII I II II I I I IIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIIIIIIIIIIIII II I II I I III II I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII II I III II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII IIIII I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I IIII IIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIIII MAXIMUM RATINGS* SymbolIIIIIIIIIIIIII Parameter VCC Vin DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) Value Unit - 0.5 to + 7.0III V V V - 0.5 to VCC + 0.5 - 0.5 to VCC + 0.5 20 25 50 750 500 Vout Iin DC Output Voltage (Referenced to GND) DC Input Current, per Pin mA mA mA Iout DC Output Current, per Pin ICC PD DC Supply Current, VCC and GND Pins Power Dissipation in Still Air Storage Temperature Plastic DIP SOIC Package mW Tstg TL - 65 to + 150 260 _C _C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. v v Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) *Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating -- Plastic DIP: -10mW/_C from 65_ to 125_C SOIC Package: -7mW/_C from 65_ to 125_C For high frequency or heavy load considerations, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). RECOMMENDED OPERATING CONDITIONS Symbol VCC Parameter Min 4.5 0 Max 5.5 Unit V V DC Supply Voltage (Referenced to GND) Vin, Vout TA DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1) VCC - 55 0 + 125 500 _C ns tr, tf DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Guaranteed Limit Symbol VIH VIL Parameter Test Conditions VCC V 4.5 5.5 4.5 5.5 4.5 5.5 4.5 4.5 5.5 4.5 5.5 5.5 - 55 to 25_C 2.0 2.0 0.8 0.8 4.4 5.4 v 85_C v 125_C 2.0 2.0 0.8 0.8 4.4 5.4 2.0 2.0 0.8 0.8 4.4 5.4 3.7 0.1 0.1 0.4 Unit V V V Minimum High-Level Input Voltage Vout = 0.1 V or VCC - 0.1 V |Iout| 20 A v v Maximum Low-Level Input Voltage Vout = 0.1 V or VCC - 0.1 V |Iout| 20 A VOH Minimum High-Level Output Voltage Vin = VIH or VIL |Iout| 20 A v v v v Vin = VIH or VIL |Iout| 4.0 mA Vin = VIH or VIL |Iout| 20 A Vin = VIH or VIL |Iout| 4.0 mA 3.98 0.1 0.1 3.84 0.1 0.1 VOL Maximum Low-Level Output Voltage V 0.26 0.33 Iin Maximum Input Leakage Current Vin = VCC or GND Vin = VCC or GND Iout = 0 A 0.1 2.0 1.0 20 1.0 80 A A ICC Maximum Quiescent Supply Current (per Package) ICC Additional Quiescent Supply Current Vin = 2.4 V, Any One Input Vin = VCC or GND, Other In uts GND Inputs lout = 0 A - 55_C 2.9 25_C to 125_C 2.4 5.5 mA NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). http://onsemi.com 2 MC74HCT74A AC ELECTRICAL CHARACTERISTICS (VCC = 5.0 V 10%, CL = 50 pF, Input tr = tf = 6.0 ns) Guaranteed Limit Symbol fmax Parameter Maximum Clock Frequency (50% Duty Cycle) (Figures 1 and 4) - 55 to 25_C 30 24 24 15 10 v 85_C 24 30 30 19 10 v 125_C 20 36 36 22 10 Unit MHz ns ns ns II I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII I II I I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIII IIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I III I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I III I I I IIII IIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I IIII IIII II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIII I I IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIII II I tPLH, tPHL tPLH, tPHL tTLH, tTHL Cin Maximum Propagation Delay, Clock to Q or Q (Figures 1 and 4) Maximum Propagation Delay, Set or Reset to Q or Q (Figures 2 and 4) Maximum Output Transition Time, Any Output (Figures 1 and 4) Maximum Input Capacitance pF NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). Typical @ 25C, VCC = 5.0 V 32 CPD Power Dissipation Capacitance (Per Enabled Output)* pF * Used to determine the no-load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). TIMING REQUIREMENTS (VCC = 5.0 V 10%, CL = 50 pF, Input tr = tf = 6.0 ns) Guaranteed Limit - 55 to 25_C v 85_C v 125_C Symbol tsu th Parameter Fig. 3 3 2 1 2 1 Min 15 3 6 Max Min 19 3 8 Max Min 22 3 9 Max Units ns ns ns ns ns ns Minimum Setup Time, Data to Clock Minimum Hold Time, Clock to Data trec tw tw Minimum Recovery Time, Set or Reset Inactive to Clock Minimum Pulse Width, Clock 15 15 19 19 22 22 Minimum Pulse Width, Set or Reset tr, tf Maximum Input Rise and Fall Times 500 500 500 http://onsemi.com 3 MC74HCT74A SWITCHING WAVEFORMS tw tr CLOCK 2.7 V 1.3 V 0.3 V tw 1/fmax tPLH Q OR Q 90% 1.3 V 10% CLOCK tTLH tTHL tPHL Q OR Q tf 3V GND Q OR Q 3V SET OR RESET 1.3 V GND tPHL 1.3 V tPLH 1.3 V trec 3V 1.3 V GND Figure 1. Figure 2. VALID 3V DATA 1.3 V GND tsu th 3V 1.3 V CLOCK *Includes all probe and jig capacitance GND DEVICE UNDER TEST TEST POINT OUTPUT CL* Figure 3. Figure 4. EXPANDED LOGIC DIAGRAM SET 4, 10 2, 12 DATA 5, 9 Q 3, 11 CLOCK 6, 8 Q 1, 13 RESET http://onsemi.com 4 MC74HCT74A PACKAGE DIMENSIONS PDIP-14 N SUFFIX CASE 646-06 ISSUE L 14 8 B 1 7 NOTES: 1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE POSITION AT SEATING PLANE AT MAXIMUM MATERIAL CONDITION. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 4. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M N INCHES MIN MAX 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 BSC 0.052 0.095 0.008 0.015 0.115 0.135 0.300 BSC 0_ 10_ 0.015 0.039 MILLIMETERS MIN MAX 18.16 19.56 6.10 6.60 3.69 4.69 0.38 0.53 1.02 1.78 2.54 BSC 1.32 2.41 0.20 0.38 2.92 3.43 7.62 BSC 0_ 10_ 0.39 1.01 A F C N H G D SEATING PLANE L J K M SOIC-14 D SUFFIX CASE 751A-03 ISSUE F -A- 14 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. -B- 1 7 P 7 PL 0.25 (0.010) M B M G C R X 45 _ F -T- SEATING PLANE D 14 PL 0.25 (0.010) K M M S J TB A S DIM A B C D F G J K M P R MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019 http://onsemi.com 5 MC74HCT74A Notes http://onsemi.com 6 MC74HCT74A Notes http://onsemi.com 7 MC74HCT74A ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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